Highly experienced Design team offers
services right from specifications to system level
Architecture design, implementaion, verification to the final
|IP/ASIC Design and
RTL Coding in Verilog and VHDL.
Verification Suite development and Automation of the verification enviornment.
Behavioral model for verification.
IP Integration at SoC Level and Verification.
RTL/Pre-Layout/Post-Layout netlist verification.
Formal Verification: RTL, netlist and at various stages of implementation.
Emulation/Target Board for ASIC/IP validation.
Porting of the Design from FPGA to ASIC.
Systemetic and Qualitative approach for FPGA implementatons.
Selection of FPGA/CPLD devices for specification, optimum speed/power performance within cost constraints.
Design and Implementation of IP blocks.
Integration of IP blocks and system level functional simulation.
Mapping Designs to target FPGA/CPLD and physical synthesis.
Expertise in emulation environment for multi-million gate System On Chip designs.
Innovative target board design techniques to enable emulation system seamless interfacing with real time test equipments and debuggers.
Exposure to Devices and EDA tools from various vendors
(XILINX, ALTERA, Lattice, Actel).
|* Xilinx is the registered trademarks of
* Altera is the
registered trademark of